This looks like a high level design entry language. It gets its portability by outputting verilog/VHDL code that is then fed into your synthesis (compiler) tools from your FPGA vendor.

There are fair number of these sorts of languages out there. Currently I'm using Altera's OpenCL kit which certainly falls into this high level design category.

The thing is that even if you're coding in a language that looks like C, you need to understand how hardware is inferred from it. Which requres a basic understanding of hardware concepts like state machines built from combinational logic and flip flops, as well as pipelining.

Bottom line on high level design... Plus side; gloss over details, focus on the workload. Down side; weird idioms, extra overhead compared to low level (i.e. Verilog).

All the HLL to HDL converters I know of require you to structure you HLL code as if it were HDL code. In other words, you are not absolved of understanding how things work at the hardware level and you can't just feed regular code into it and have it pop out hardware.

If you have to write stilted HLL to implement your design anyway, you might as well do it properly and write it in one of the HDLs instead.